At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We have an immediate opening in the Post Silicon Physical Layer Electrical Validation team at Cadence Design Systems Bangalore, for the post of ” Design Engineer”.
The responsibility entails performing pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation primarily on Cadence’s High Speed SERDES Test chips, ie, activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc.
Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.
• 0-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
• Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.
• Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
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To apply for this job please visit cadence.wd1.myworkdayjobs.com.